1. Field of the Invention
The present invention relates to amplifier circuits, and particularly to amplifier circuits having distributed parallel amplifier stages.
2. Description of the Related Art
Amplifier circuits sometimes include an amplifier stage that is implemented with multiple parallel transistors instead of just one transistor. For example, a precision differential amplifier circuit may include a differential pair of transistors in a first amplifier stage. Each of two transistors forming this differential pair may actually be implemented as multiple (e.g., four, eight, or sixteen) individual transistors connected in parallel. However, individual transistors of both the first and second differential pair transistors are spatially intermixed with each other in a two dimensional array. In this fashion, differences in transistor characteristics that result from a gradient of a parameter across the semiconductor device tend to cancel out and result in a lower offset voltage of the differential amplifier. Such gradients could include variations in doping density, temperature, electrical or magnetic field, mobility, threshold voltage, and others. Such multiple devices in an amplifier circuit are usually implemented in a tight localized area to minimize the magnitude of any parametric differences caused by the gradient thereacross, even though the interspersed physical arrangement is helpful in reducing (or even canceling out) the effects of such gradients on the offset of the amplifier.
In other amplifiers, such multiple parallel stages may be spatially distributed across a large area of a circuit. For example, an amplifier may be configured to deliver a high current to an output node which traverses a large area of an integrated circuit, but such output current may be drawn out locally at any location along the output node. In such a case, distributing the final amplifier stage (or driver stage) over a wide area places many of the final stages closer to the actual output current load. This can reduce the output node sensitivity to wiring resistance, noise coupling, and other effects.
Referring now to FIG. 1, an amplifier circuit 100 generates an output signal on an amplifier output node 102 which is distributed throughout a memory array 104. Two amplifiers are shown, one at the bottom of the figure, and the other at the top of the figure. The first amplifier includes a plurality of spatially distributed output driver NMOS transistors 116, 117, 118, each of which has a drain terminal coupled to a power supply node (e.g., here shown as a VDD node), a gate terminal coupled to a CTRL_A control node 114, and a source terminal coupled to the amplifier output node 102. When this amplifier is enabled by an ENABLE_A signal conveyed on node 112 (i.e., also referred to as the “enable 112” signal), the amplifier output node 102 is compared against a reference voltage VREF_A conveyed on node 113, and the CTRL_A signal 114 is generated accordingly. The distributed NMOS driver transistors 116, 117, 118 are in a source follower configuration, with the amplifier output node 102 voltage being lower than the CTRL_A voltage.
The second amplifier includes a plurality of spatially distributed output driver PMOS transistors 126, 127, 128, each of which has a drain terminal coupled to the power supply node, a gate terminal coupled to a CTRL_B control node 124, and a source terminal coupled to the amplifier output node 102. When this amplifier is enabled by an ENABLE_B signal conveyed on node 122 (i.e., also referred to as the “enable 122” signal), the amplifier output node 102 is compared against a reference voltage VREF_B conveyed on node 123, and the CTRL_B signal conveyed on node 124 is generated accordingly. The distributed PMOS driver transistors 126, 127, 128 are in a common gate amplifier configuration, with the amplifier output node 102 voltage being higher than the CTRL_B voltage.
Many integrated circuits utilize tungsten metallization for interconnect wiring, particularly if high temperature operations are required after deposition of such a wiring layer. Such tungsten interconnect lines have a much higher resistance (e.g., 1.3 Ohms/square) than aluminum or copper-doped aluminum (e.g., 0.04 Ohms/square). Certain 3D memory architectures may require using tungsten for power distribution under the memory array because of the high temperatures required to form memory cells on each of the multiple memory planes. In addition, diode-based memory arrays may require regulating the unselected word line and unselected bit line voltages in the selected array blocks. Due to the reverse current of the unselected diodes, a substantial current may flow through the unselected memory cells while regulating the voltage of the unselected word lines and unselected bit lines. This current can be concentrated in a very small area, yet the particular area of current flow can occur anywhere within the array (i.e., over a wide range of area).
Using an amplifier with distributed drivers (i.e., more generally “final amplifier stages”) alleviates these problems, as it can provide very low output resistance somewhat independent from the position of the current load (i.e. from the position of the selected array block). If different voltage levels are required for read or write, two different amplifiers may be utilized, sharing the same output node, but each with multiple drivers distributed throughout the array (i.e. one for read, one for write, as in the above example). Each such amplifier requires a sensitive controlling node to drive its group of drivers. As memory array become increasingly dense, routing each of the control nodes becomes more difficult. This is particularly true in a three-dimensional memory array where routing freedom is limited.